Design of a Cmos 6-bit Folding and Interpolating Analog to Digital Converter

This thesis describes the design of a 6-bit CMOS folding and interpolating Analog to Digital Converter (ADe). Folding and interpolating techniques can be used in CMOS flash type ADCs so that less die area and power dissipation are used. while at the same time maintaining high-speed operation. The fundamentals of the CMOS folding and interpolating circuits are covered, and some of the major design issues are reviewed and discussed. Simulation and experimental results from a 6-bit ADe test chip fabricated in a I .2um process are also presented.